1. Field of the Invention
This invention relates to a semiconductor device manufacturing method, and particularly to a method for inhibiting dummy cell over-erase in a memory device.
2. Background of the Invention
A memory device conventionally may include a transistor that serves as a memory cell coupled to a word line and a bit line. A conventional nitride read only memory (NROM) cell includes a substrate having a source region spaced-apart from a drain region, and a channel region therebetween. The NROM cell also includes an oxide-nitride-oxide (ONO) structure formed over the channel region and portions of the source and drain regions. The ONO structure includes a first oxide layer formed over the substrate, a nitride layer formed over the first oxide layer, and a second oxide layer formed over the nitride layer. The NROM cell further includes a gate structure formed over the second oxide layer, and sidewall spacers formed contiguous with at least the gate structure. The nitride layer xe2x80x9cstores xe2x80x9d electrical charges by trapping electrons therein, and the thickness of the first and second oxide layers should be sufficient to prevent leakage, i.e., direct tunneling of stored electrons under normal operating conditions.
Multiple memory cells, including the NROM cells, may form a memory array, which generally includes the memory cells coupled to a grid of word lines and bit lines. During formation of the memory device, the memory lines (word lines and bit lines) at the edges of the device are often etched partially or completely, rendering unusable the memory cells to which they are connected. To protect a usable memory cell from damage, the memory device may include, at an edge, a dummy word line (i.e., a word line not used for programming). The dummy word line may not be coupled to a word line driver, thus each memory cell connected to the dummy word line will not be used to store dataxe2x80x94i.e., it is a dummy cell. Consequently, etching of the dummy word line during formation will not result in loss of usable memory.
Conventionally, the dummy word line at the edge is continuously coupled to ground. Thus, regardless of the voltage applied to a corresponding bit line (whether a program or erase voltage), the dummy cell is in a constant state of being weakly erased, which leads to over-erasure of the dummy cell in certain situations. In addition, the state of the dummy cells may result in bit line to bit line current leakage both in the dummy cells and the memory cells during read operations of the memory cells.
In accordance with the present invention, there is provided a semiconductor device that includes a semiconductor substrate including a memory cell region and a dummy cell region, a plurality of substantially parallel bit lines in the semiconductor substrate, a plurality of memory cell gate dielectrics provided over the bit lines in the memory cell region, the memory cell gate dielectrics comprising an oxide-nitride-oxide (ONO) layer, a plurality of dummy cell gate dielectrics provided over the plurality of bit lines in the dummy cell region, wherein the dummy cell gate dielectrics is non-trapping for electric charges, and a plurality of substantially parallel word lines over the memory cell gate dielectrics and the dummy cell gate dielectrics.
Also in accordance with the present invention, there is provided a method for manufacturing a semiconductor device that includes providing a semiconductor substrate, providing a memory cell region and a dummy cell region in the semiconductor substrate, forming a plurality of bit lines in the semiconductor substrate, providing an oxide-nitride-oxide layer over the plurality of bit lines in the memory cell region, providing a layer of non-trapping material over the plurality of bit lines in the dummy cell region, wherein the non-trapping material comprises an oxide, and providing a plurality of word lines over the oxide-nitride-oxide layer and the layer of non-trapping material in the memory cell region and the dummy cell region.
Still in accordance with the present invention, there is provided a method for manufacturing a semiconductor device that includes providing a semiconductor substrate, providing a memory cell region and a dummy cell region in the semiconductor substrate, forming at least one memory cell in the memory cell region, including providing a first source region and a first drain region in the semiconductor substrate, providing an oxide-nitride-oxide layer over the first source and drain regions, patterning and etching the oxide-nitrde-oxide layer to form at least one gate dielectric, and providing a first gate over the at least one gate dielectric, and forming at least one dummy cell in the dummy cell region, including providing a second source region and a second drain region in the semiconductor substrate, providing a layer of non-trapping material over the second source and drain regions, wherein the non-trapping material comprises silicon dioxide or aluminum oxide, patterning and etching the first oxide layer of non-trapping material to form at least one dummy gate dielectric, and providing a second gate over the layer of non-trapping material.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.